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Features
* 80C52 Compatible
- 8051 pin and instruction compatible - Four 8-bit I/O ports + 2 I/O I2C Interface pins - Three 16-bit timer/counters - 256 bytes scratch pad RAM - 10 Interrupt sources with 4 priority levels - Dual Data Pointer Variable length MOVX for slow RAM/peripherals ISP (In System Programming) using standard VCC power supply. Boot ROM contains low level FLASH programming routines and a default serial loader High-Speed Architecture - 40 MHz in standard mode - 20 MHz in X2 mode (6 clocks/machine cycle) 32-Kbytes on-chip FLASH program / data Memory - Byte and page (128 bytes) erase and write - 10k write cycles - On-chip 1024 bytes expanded RAM (XRAM) - Software selectable size (0, 256, 512, 768, 1024 bytes) - 256 bytes selected at reset for T87C51RB2/RC2 compatibility Keyboard interrupt interface on port P1 400-Kbits/s Multimaster I 2C Interface SPI Interface (Master / Slave Mode) Sub clock 32kHz crystal oscillator 8-bit clock prescaler Improved X2 mode with independant selection for CPU and each peripheral Programmable Counter Array 5 Channels with: - High Speed Output, - Compare / Capture, - Pulse Width Modulator, - Watchdog Timer Capabilities Asynchronous port reset Full duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (inhibit ALE) Hardware Watchdog Timer (One-time enabled with Reset-Out) Power control modes: - Idle Mode. - Power-down mode. - Power-Off Flag. Power supply: 4.5V to 5.5V or 2.7V to 3.6V Temperature ranges: Commercial (0 to +70C) and industrial (-40C to +85C). Packages: PLC44, VQFP44
* * * * *
8-bit Microcontroller with Flash and I2C Interface
* * * * * * *
T89C51IC2 Summary
* * * * * *
* * *
Description
T89C51IC2 is a high performance FLASH version of the 80C51 8-bit microcontrollers. It contains a 32-Kbytes Flash memory block for program and data. The 32-Kbytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C51IC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7source 4-level interrupt controller and three timer/counters.
Rev. C - 3-Dec-01
1
In addition, the T89C51IC2 has a 32kHz Subsidiary clock Oscillator, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a I2C Interface, a SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The fully static design of the T89C51IC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51IC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51IC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. Table 1. Memory Size
PLCC44 VQFP44 1.4 T89C51IC2 Flash (bytes) 32k XRAM (bytes) 1024 TOTAL RAM (bytes) 1280 I/O 34
Block Diagram
T2EX RxD PCA TxD T2
SDA
(2) (2) XTAL1 XTAL2
ECI
(1)
( 1) (1)
(1)
EUART + BRG
RAM 256x8
F las h 32K x8 or 16K x8
XRAM
1Kx8
Boot ROM 2Kx8
PCA
Timer2
I2C
ALE/ PROG PSEN CPU EA RD WR ( 2) ( 2)
C51 CORE
IB-bus
Timer 0 Timer 1
INT Ctrl
Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3Port I2
Watch Key Dog B oard
SPI
(2) (2) RESET T0 T1
(2) ( 2) PI2 P1 P2 P3 INT0 INT1 P0
(1) (1) (1) ( 1) MISO MOSI SCK
(1): Alternate function of Port 1 (2): Alternate function of Port 3
2
T89C51IC2
Rev. C - 3-Dec-01
SS
SCL
Vss
VCC
T89C51IC2
SFR Mapping
The Special Function Registers (SFRs) of the T89C51IC2 fall into the following categories: * * * * * * * * * * * * * * * * C51 core registers: ACC, B, DPH, DPL, PSW, SP I/O port registers: P0, P1, P2, P3, PI2 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) Power and clock control registers: PCON Hardware Watchdog Timer registers: WDTRST, WDTPRG Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 Keyboard Interface registers: KBE, KBF, KBLS SPI registers: SPCON, SPSTR, SPDAT I2C Interface registers: SSCON, SSCS, SSDAT, SSADR BRG (Baud Rate Generator) registers: BRL, BDRCON Flash register: FCON Clock Prescaler register: CKRL 32Khz Sub Clock Oscillator registers: CKSEL, OSSCON Others: AUXR, AUXR1, CKCON0, CKCON1
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Rev. C - 3-Dec-01
Table 2. SFR mapping Table below shows all SFRs with their address and their reset value.
Bit addressable 0/8 F8h B 0000 0000 CL 0000 0000 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 T2CON 0000 0000 PI2 bit addressable XXXX XX11 B8h IPL0 X000 000 P3 1111 1111 IE0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A SBUF XXXX XXXX SADEN 0000 0000 IE1 XXXX X000 SADDR 0000 0000 AUXR1 XXXX X0X0 BRL 0000 0000 BDRCON XXX0 0000 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 3/B 4/C KBLS 0000 0000 SSCS 1111 1000 TH0 0000 0000 KBE 0000 0000 SSDAT 1111 1111 TH1 0000 0000 CKSEL XXXX XXX0 5/D WDTRST XXXX XXXX KBF 0000 0000 SSADR 1111 1110 AUXR XX0X 0000 OSSCON XXXX X001 6/E CKRL 1111 1111 CKCON0 0000 0000 PCON 00X1 0000 7/F IPL1 XXXX X000 IPH1 XXXX X111 IPH0 X000 0000 CKCON1 XXXX XXX0 WDTPRG XXXX X000 CMOD 00XX X000 FCON (1) XXXX 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 SPCON 0001 0100 TL2 0000 0000 SPSTA 0000 0000 TH2 0000 0000 SPDAT XXXX XXXX CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 CCAP0L XXXX XXXX CCAP1L XXXX XXXX CCAPL2L XXXX XXXX CCAPL3L XXXX XXXX CCAPL4L XXXX XXXX 1/9 CH 0000 0000 2/A CCAP0H XXXX XXXX 3/B CCAP1H XXXX XXXX Non Bit addressable 4/C CCAPL2H XXXX XXXX 5/D CCAPL3H XXXX XXXX 6/E CCAPL4H XXXX XXXX 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h C8h
D7h CFh
C0h
C7h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
reserved
(1) FCON access is reserved for the FLASH API and ISP software.
4
T89C51IC2
Rev. C - 3-Dec-01
T89C51IC2
Pin Configurations
P1.0/T2/XTALB1
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI RST P3.0/RxD PI2.1/SDA P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA PI2.0/SCL ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
PLCC44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR P2.2/A10
P0.1/AD1
P1.0/T2/XTALB1
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
P0.0/AD0
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI RST P3.0/RxD PI2.1/SDA P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA PI2.0/SCL ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
VQFP44 1.4
12 13 14 15 16 17 18 19 20 21 22
P2.2/A10 P2.3/A11 XTAL1 P3.7/RD P2.0/A8 P2.4/A12 P3.6/WR P2.1/A9 XTAL2 NIC* VSS
P0.3/AD3
P1.2/ECI
XTALB2
VCC
P2.3/A11 P2.4/A12
P3.7/RD
NIC* P2.0/A8
P2.1/A9
XTAL2
XTAL1
VSS
P0.2/AD2 P0.3/AD3
P0.0/AD0
P0.1/AD1
P1.2/ECI
XTALB2
VCC
5
Rev. C - 3-Dec-01
Table 1. Pin Description for 40/44 pin packages
Pin Number Type Mnemonic VSS VCC P0.0-P0.7 PLCC44 22 44 43-36 VQFP44 1.4 16 38 37-30 I I I/O Ground: 0V reference Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for T89C51IC2 Port 1 include: 2 40 I/O I/O I 3 41 I/O I I 4 42 I/O I 5 43 I/O I/O 6 44 I/O I/O 7 1 I/O I/O I/O P1.0: Input / Output T2 (P1.0): Timer/Counter 2 external count input/Clockout XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier P1.1: Input / Output T2EX: Timer/Counter 2 Reload/Capture/Direction Control SS: SPI Slave Select P1.2: Input / Output ECI: External Clock for the PCA P1.3: Input / Output CEX0: Capture/Compare External I/O for PCA module 0 P1.4: Input / Output CEX1: Capture/Compare External I/O for PCA module 1 P1.5: Input / Output CEX2: Capture/Compare External I/O for PCA module 2 MISO: SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. 8 2 I/O I/O I/O P1.6: Input / Output CEX3: Capture/Compare External I/O for PCA module 3 SCK: SPI Serial Clock SCK outputs clock to the slave peripheral 9 3 I/O P1.7: Input / Output: Name and Function
P1.0-P1.7
2-9
40-44 1-3
I/O
6
T89C51IC2
Rev. C - 3-Dec-01
T89C51IC2
Pin Number Type Mnemonic PLCC44 VQFP44 1.4 I/O I/O Name and Function CEX4: Capture/Compare External I/O for PCA module 4 MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. XTALA1 XTALA2 XTALB1 21 20 2 15 14 40 I O I Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal A 2: Output from the inverting oscillator amplifier Crystal B 1: (Sub Clock) Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal B 2: (Sub Clock) Output from the inverting oscillator amplifier Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for 16Kb devices P2.0 to P2.6 for 32Kb devices P3.0-P3.7 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port I2: Port I2 is an open drain. It can be used as inputs (must be polarized to Vcc with external resistor to prevent any parasitic current consumption). I/O SCL (PI2.0): I2C Serial Clock SCL output the serial clock to slave peripherals SCL input the serial clock from master 12 6 I/O SDA (PI2.1): I2C Serial Data SDA is the bidirectional I2C data line
XTALB2 P2.0-P2.7
1 24-31
39 18-25
O I/O
11 13 14 15 16 17 18 19 PI2.0-PI2.1 34, 12 34
5 7 8 9 10 11 12 13 28, 6 28
I O I I I I O O
7
Rev. C - 3-Dec-01
Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Strobe ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset.
RST
10
4
I/O
ALE/PROG
33
27
O (I)
PSEN
32
26
O
EA
35
29
I
8
T89C51IC2
Rev. C - 3-Dec-01
T89C51IC2
Ordering Information
Table 2. Possible order entries
Flash Memory Size 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes Supply Voltage 5V 5V 3V 5V 3V Temperature Range Commercial Industrial Industrial Industrial Commercial Max Frequency 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz
Part Number T89C51IC2-SLSCM T89C51IC2-SLSIM T89C51IC2-SLSIL T89C51IC2-RLTIM T89C51IC2-RLTIL
Package PLCC44 PLCC44 PLCC44 VQFP44 VQFP44
Packing Stick Stick Stick Tray Tray
Note:
Purchase of Atmel I2C components conveys a license under the Philips I2C Patent's right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
9
Rev. C - 3-Dec-01
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